Scaling of Aligned Carbon Nanotube Transistors Achieved at Sub-10 nm Nodes by Researchers

Scaling of Aligned Carbon Nanotube Transistors Achieved at Sub-10 nm Nodes by Researchers

Carbon‍ nanotubes, large cylindrical ‌molecules composed of hybridized carbon atoms arranged in a hexagonal structure, recently attracted significant attention among⁣ electronics⁢ engineers. Due ‍to their geometric configuration and advantageous⁢ electronic properties,‌ these ⁢unique ⁤molecules could be⁤ used to create smaller field-effect transistors (FETs) that exhibit⁣ high energy efficiencies.

FETs based on carbon nanotubes have⁤ the potential to ​outperform smaller transistors based on silicon, yet their advantage in real-world implementations has yet to ‌be ‌conclusively demonstrated. A‌ recent paper by researchers at Peking University and other⁤ institutes in China, published in⁤ Nature Electronics, outlines ​the realization of FETs based on carbon nanotubes that can be scaled to the same size of a 10 nm silicon technology ‌node.

“Recent progress ‌in achieving wafer-scale high density semiconducting carbon nanotube arrays brough us one step closer ‌to‌ the practical use⁤ of carbon nanotubes in CMOS circuits,”⁢ Zhiyong Zhang, one ⁢of the researchers who ‍carried out the study, told Phys.org. “However, previous research‌ efforts have mainly ⁣focused ‌on the scaling of ‌channel or gate‌ length​ of carbon ‌nanotube transistors while keeping⁤ large‍ contact dimensions, which cannot be accepted for high density ‍CMOS circuits in practical⁢ applications.

“Our⁤ primary objective of this work‍ is to explore the true scaling capability of carbon nanotube arrays using two figures of merit in silicon industry, that ⁢is, contacted gate pitch and​ area of ⁤6T SRAM cell, while maintaining the performance advantages.”

Zhang⁢ and‌ his colleagues essentially set out to demonstrate the practical value of carbon nanotube ​transistors, showing⁣ that they⁢ can outperform conventional silicon-based FETs with a‍ comparable⁤ gate⁤ pitch ⁣and a 6T SRAM​ cell area. To achieve this, they first fabricated FETs based on carbon nanotube arrays with a contacted gate pitch of 175 nm. This gate ‍pitch was realized by scaling ⁤the gate length and contact length ​to 85 nm and‌ 80 nm, respectively.

2023-07-27 16:00:04
Source from phys.org

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